The delay-locked loop circuit (hereinafter to be referred to as DLL circuit) is a circuit that generates any signal phase locked to a clock signal or the like. FIG. 22 is a diagram illustrating an example of the constitution of a DLL circuit of the prior art. The DLL circuit shown in FIG. 22 has delay line 1, phase detector (phase comparator) 2, charge pump 3, and low-pass filter 4. Said delay line 1 delays input clock signal φin and outputs a delayed signal. The delay time of delay line 1 can be changed corresponding to control voltage V1f. Said phase detector 2 detects the phase difference between clock signal φin input to delay line 1 and clock signal φout (φdin), and it generates signals (Vup, Vdn) corresponding to the phase difference. Said charge pump circuit 3 outputs current Ipd corresponding to the signals (Vup, Vdn) as the phase detection result output from phase detector 2. Low-pass filter 4 smooths current Ipd output from charge pump circuit 3 and converts it to control voltage V1f. 
The basic function of the DLL circuit is to provide a prescribed delay by delay line 1 for input clock signal φin. The output current Ipd of charge pump circuit 3 is smoothed by low-pass filter 4, and it is then sent as control voltage V1f to delay line 1. The delay of delay line 1 is controlled corresponding to said control voltage V1f. Said control voltage V1f is determined as follows. When the phase of clock signal φdin lags behind clock signal pin, said phase detector 2 generates signal Vup having a pulse width corresponding to the delay quantity of the phase (FIG. 23). Conversely, when the phase of clock signal φdin is ahead of clock signal φin, phase detector 2 generates signal Vdn having a pulse width corresponding to the advance quantity of the phase (FIG. 24). The advance or delay in the phase detected by phase detector 2 is judged by comparing the rising edges of the two clock signals (φin, φdin). For example, as shown in FIG. 23, for the two rising edges as the objects for comparison, assume that the edge of clock signal φdin is generated behind the edge of clock signal φin (FIGS. 23(A), (B)). In this case, phase detector 2 judges that the phase of clock signal φdin lags behind clock signal φin, and it generates signal Vup (FIG. 23(C)).
On the other hand, as shown in FIG. 24, for the two rising edges as the objects for comparison, assume that the edge of clock signal φdin is ahead of the edge of clock signal φin (FIGS. 24(A), (B)). In this case, phase detector 2 judges that the phase of clock signal φdin is ahead of clock signal φin, and it generates signal Vdn (FIG. 24(D)).
In FIGS. 23 and 24, “Δφ” indicates the phase difference between clock signal φin and clock signal φdin detected by phase detector 2. When phase difference Δφ is positive, clock signal φdin lags behind clock signal φin, and when phase difference Δφ is negative, clock signal φdin is ahead of clock signal φin. Also, because clock signal φdin is a signal obtained by delaying clock signal φin via delay line 1, in consideration of this delay, the phase of clock signal φdin cannot be ahead of the phase of clock signal φin. The “advance in phase” and “delay in phase” detected by phase detector 2 is determined by the give-and-take relationship between the two rising edges as the objects for comparison, and it may not be in agreement with the actual delay of clock signal φdin with respect to clock signal φin.
While phase detector 2 outputs Vup, charge pump circuit 3 feeds current Ip to low-pass filter 4 during the period. By means of this current Ip, a capacitor (not shown in the figure) contained in low-pass filter 4 is charged, and control voltage V1f output from low-pass filter 4 rises. On the other hand, while phase detector 2 outputs signal Vdn, charge pump circuit 3 pulls current Ip from low-pass filter 4 during this period. By means of this current Ip, the capacitor contained in low-pass filter 4 discharges, and control voltage V1f output from low-pass filter 4 falls.
When the capacitance of this capacitor is “Cp,” control voltage V1f can be represented by the following formula.
                    [                  Mathematical          ⁢                                          ⁢          formula          ⁢                                          ⁢          1                ]                                                                                  V                          1              ⁢              f                                ⁡                      (            t            )                          =                                            I              p                                      2              ⁢              π              ⁢                                                          ⁢                              C                p                                              ⁢          t          ⁢                                          ⁢          Δϕ          ⁢                                          ⁢                      u            ⁡                          (              t              )                                                          (        1        )            
In formula (1), “u(t)” represents a step function.
The delay of delay line 1 decreases as control voltage V1f increases, and it increases as control voltage V1f decreases. In this case, when phase difference Δφ is positive (the phase of clock signal φdin lags), in phase detector 2, signal Vup is generated, control voltage V1f increases, and the delay of delay line 1 decreases. On the other hand, when phase difference Δφ is negative (phase of clock signal φdin is ahead), phase detector 2 generates signal Vdn, control voltage V1f decreases, and the delay of delay line 1 increases. Due to said operation, in the DLL circuit shown in FIG. 22, when the phase of clock signal φin and the phase of clock signal φdin come into agreement as detected by phase detector 2, a stable state (hereinafter to be referred to as locked state) results. In this case, the phase difference Δφ between clock signal φin and clock signal φdin is “2π,” (where n is an integer). Usually, delay line 1 is formed by connecting plural inverters or other delay elements in tandem. Consequently, for example, when the DLL circuit is controlled such that the phase difference between input/output is delay line 1 of “2π,” plural clock signals can be obtained that have different phase differences from “0” to “2π” with respect to clock signal φin.
FIG. 25 is a diagram illustrating an example of signals output from the delay elements when delay line 1 is formed by connecting, in tandem, four delay elements having the same delay. In the example shown in FIG. 25, the DLL circuit is controlled such that the phase difference between the input and output of delay line 1 becomes “2π.” In this case, the phase difference between the delay elements with respect to clock signal φin sequentially becomes “π/2,” “π,” “3π/2,” and “2π” from the initial stage. The signals output from the delay elements have their phases shifted from each other by “π/2.”
In the DLL circuit shown in FIG. 22, control is performed such that phase difference Δφ between clock signal φin and clock signal φdin is “2π.” Consequently, when integer n changes, all of the signals output from the various delay elements of delay line 1 change, and this is a problem. In the example shown in FIG. 25, a locked state occurs with a phase difference between clock signal φin and clock signal φdin of “2π,” and integer n is “1.” However, for the DLL circuit shown in FIG. 22, a locked state also can be obtained when integer n is not “1.”
FIG. 26 is a diagram illustrating an example of the output signal of the delay element when the phase difference between clock signal φin and clock signal φdin is “4π” in the locked state (that is, when integer n is “2”) in the DLL circuit having delay line 1 comprised of four delay elements in the same way as shown in FIG. 25. In this case, signals φ1˜φ4 output from the delay elements shift in phase from each other by “π,” and the apparent phase difference with respect to clock signal φin becomes “0” or “π.” As shown in FIG. 25, this state is entirely different from the state of signals φ1˜φ4 with phases shifted from each other by “π/2.”
In the following, an explanation will be given on this problem from another viewpoint. FIG. 27 is the relationship between detected phase difference Δφ detected in phase detector 2 as abscissa and output current Ipd of charge pump circuit 3 as ordinate. Said phase detector 2 and charge pump circuit 3 operate along the solid lines in FIG. 27. When the phase difference Δφ in the initial state is in the range of “+2π<Δφ<+4π,” because the phase of clock signal φdin lags behind the phase of clock signal φin, signal Vup is generated in phase detector 2 so as to drive the phase of clock signal φdin ahead, and control is performed for the system until “Δφ=+2π.” Consequently, the DLL circuit reaches the locked state at point A as shown in FIG. 27. In this case, the phase difference between clock signal φin and clock signal φdin becomes “2π,” so that normal signals as shown in FIG. 25 are output from the various delay elements of delay line 1.
With an initial state of “0<Δφ<+2π,” the phase of clock signal φdin lags behind clock signal φin, so that signal Vup is generated in phase detector 2, and the system is controlled such that “Δφ=0.” Consequently, the DLL circuit reaches the locked state at point B as shown in FIG. 27. Because the delay of delay line 1 is not strictly zero, the DLL circuit becomes stable while control is continued so that it is locked at point B. Even if the initial state is “−2π<Δφ<0,” because the system is controlled such that “Δφ=0,” the DLL circuit becomes locked at point B as shown in FIG. 27. With an initial state of “+4π<Δφ<+6π,” the system is controlled such that “Δφ=+4π,” and the DLL circuit reaches the locked state at point C as shown in FIG. 27. In this case, for example, the delay elements of delay line 1 generate abnormal signals as shown in FIG. 26. The aforementioned abnormal locked state is generated corresponding to the initial state of phase difference Δφ when the DLL circuit is started. In addition, it also takes place in some other cases during the operation of the DLL circuit, such as when the operation departs from the locus of the intrinsic feedback control due to external noise, etc., and when there is a significant change in the frequency of clock signal φin.
FIG. 28 is a diagram illustrating an example of change in the lock state due to a change in the frequency of clock signal φin. It can be seen that although the lock state is normal at a certain frequency (n=1), the lock state becomes abnormal when the frequency of clock signal φin is changed and doubled (n=2). In the example shown in FIG. 28, the lock state shifts from point A shown in FIG. 27 to point C. For the DLL circuit, when operation continues in said abnormal lock state, the circuit that operates based on the clock signal generated by DLL circuit becomes unstable, so that mis-operation takes place, and the power consumption rises due to waste. This is undesirable.
A general object of the present invention is to solve the aforementioned problems of the prior art by providing a type of delay-locked loop circuit that can prevent an abnormal lock state during start-up. Another general object of the present invention is to provide a type of delay-locked loop circuit that can prevent continuous operation in an abnormal lock state.